The present invention relates to a fault-compensating digital information transfer apparatus and, more particularly, to a fault-tolerant digital information transfer apparatus for transferring digital information among function modules fabricated on a semiconductor chip.
As an example of the prior art, consider a case in which the function modules, e.g. CPUs and I/O devices, of a computer system have intelligent processors. Normally, digital information is transferred in parallel among the function modules over a common bus. Noise occurring in the common bus occasionally invalidates the digital information during this transfer. A number of design measures have been taken in the past to identify and correct these transfer errors. For example, one such measure includes transferring the same data repeatedly. Another measure uses error correction data (e.g., one or more parity bits) attached to part of each data word. These measures can effectively check minor isolated transfer errors, but cannot accomodate or correct major transfer errors arising, for example, from the disconnection of the common bus from the function modules.
To cope with such major errors, one recently proposed approach uses a first common bus and a second or backup common bus in the computer system. In this approach, if the first common bus is disconnected, it is replaced by the second or backup common bus. As a result of this replacement, the transfer operation is rapidly returned from a nonoperative state to an operative state.
Recent advances in semiconductor fabrication technology have enabled the function modules to be fabricated as a single LSI device on a single LSI chip, rather than a printed circuit board. However, fabrication of both the first and second common buses on the same semiconductor chip is undesirable because the dual common buses occupy a large area on the semiconductor chip. The result of placing both common buses on a single chip is that a correct, secure transfer of data occurs, but the remaining area of the chip is insufficient for fabrication of the function modules. This problem can be avoided by using a larger semiconductor chip, but this approach increases the difficulty of further miniaturization of the LSI chip.